As is known in the art, Field Effect Transistors (FETs) having a linear array of a plurality of FET cells are used in many applications. Each one of the FET cells has a source, a drain and a gate between the source and the drain to control a flow of carriers along a channel between the source and drain. In some FETS, as for example, shown in FIG. 1, the gates are finger-like gates (GF) interconnected to a common gate contact (GC) on the top surface of a substrate. Likewise, the drains are individual drain fingers (DF) connected to a common drain contact (DC) electrode on the top of the substrate, and the sources are source pads (S) on the top of the substrate and are connected to a common source contact, not shown, on the bottom of the substrate using interconnected air bridges, each air-bridge being over the a pair of gate fingers (GF) and one drain finger (DF) between a pair of gate fingers (GF), the ends of the interconnected air bridges being connected the common source contact, not shown, on the bottom surface of the substrate using vias that pass through the substrate to the common source contact, not shown, on the bottom surface of the substrate. Generally, many of these are FET cells are stacked together in a linear array, here along the Y-axis in FIG. 1, in the output stage of a power amplifier Monolithic Microwave Integrated Circuit (MMIC). The linear stacking of these FET cells determines the linear dimension size of the MMIC.